iASIC Design Through Production
For more than 30 years, JVD has been supplying the electronics industry with high performance, cost effective, mixed signal ASIC solutions. JVD has developed a reputation of quality and cost consciousness. Our core engineering team alone boasts more than 300 years of Analog IC design experience.
We take the words “Application Specific” seriously. We believe the “cookie cutter” approach of force-fitting a mixed signal design into a standard cell library may not always provide the best result for our customers. At JVD, we offer fully customized designs that can be targeted at various Bipoloar, CMOS, and BiCMOS processes, guaranteeing you the best cost/performance match for your application.
Step 1: Establishing Specifications
Customers meet with JVD engineers to review the requirements of the application. Design methodologies are discussed, including those that will facilitate the successful testing of the final chip. When the specification is completed, including functional blocks, pin-outs, packaging, process requirements, and critical performance parameters, a quotation is made that then forms the basis for a development contract.
Step 2: Design and Verification
JVD uses the latest analog simulation and verification tools from OrCAD PSpice, DW-2000, Altium Designer to mitigate any risk. When possible, the critical aspects of the design are prototyped prior to releasing the design to layout. It is important to verify that the design performs correctly in a real application environment as well as in simulation.
Upon completion of the design and verification phases, a milestone meeting with the customer takes place. Upon customer approval, the design and then the project moves forward to the layout phase.
Step 3: IC Layout
At this stage, any special ESD cells required by the design are generated as well as any unique I/O structures. Mixed signal layout is tricky and often managed by hand to ensure optimal circuit performance and density. When the layout is complete, the device signal chain analysis is simulated under different process, temperature and voltage parameters, with particular attention paid to noise, capacitance, and parasitics. With a milestone approval from the customer, a GDSII “tape” is generated for the mask production.
Step 4: Mask Generation
Mask generation typically takes place at the silicon foundry. A mixed signal chip may have as many as 25 -30 masks (photographic plates used in the process). An inspection of the masks is made by JVD before the masks are released to foundry.
Step 5: Manufacture Initial Samples
With the release of the masks, the foundry produces a batch of engineering prototype wafers – usually 6 to 12 wafers. Usually, some wafers are retained for setting up probe and test in preparation for mass production. The others are processed into individual die and assembled into packages for ease of qualification of the part. The packages are supplied to the customer to verify their operation in the customer’s application.
Step 6: Test Development
Although identified here as Step 6, test development is a parallel activity that begins at the same time as the Design (Step 2), as it can take as long or longer to complete as the chip design itself. Test hardware and software must be at or near completion when the first prototype silicon arrives. Both the silicon and the automatic production tester undergo simultaneous debugging.
Step 7: Production
Once the initial samples have been qualified at the third and last milestone meeting, JVD prepares the tooling and probe test cards to manufacture and deliver production silicon.
Step 8: Lifetime Product Support
Throughout the product life, JVD’s technical and manufacturing experts support the design and manufacturing requirements of the product. JVD maintains inventory to ensure timely delivery of parts.
Step 9: Second Sources, Next Generation Products
Often, once a product is in production, an additional wafer fab is brought on as a second source to ensure secure deliveries of high volume products. The second source fab usually requires a new set of masks and JVD handles the adaptation of the design and qualification for the slight differences in process. In addition, it is often the case that JVD will design variations of the iASIC for the customer’s family of products. Some of JVD’s products have been in continuous production for over fifteen years. Eventually a new design may be required to take advantage in advances in technology and JVD ensures a seamless transition into the new product. JVD is always seeking to improve performance or reduce cost of custom iASICS’s in next generation products.