FAQ: Frequently Asked Questions
Converting a design from standard components to a custom device is never an easy decision. There are serious pros and cons and you should weigh them carefully before committing. Let’s examine a few here:
Reliability: Some will argue that reducing part and connectivity count will improve the reliability of the system. This was more true 20 or 30 years ago than today. With the advanced level of manufacturing techniques available today from the global contract manufacturers, failure rates are already very low. Yes, you will see improvement but it is more a third or fourth order effect in the decision process.
Performance, cost and size reduction are often cited as the main drivers for creating an iASIC. Study your situation carefully to determine if the combination of these benefits makes your design/application worthy of integration. It is likely that when viewed individually, the benefits are marginally better, but when taken in their entirety, the choice will become obvious. Standard Analog ICs offer a wide range of performance, and those at the high end are priced accordingly… because the market will bear it. Quite honestly, there is minimal if any cost differential to manufacture a standard product versus its high performance sibling. When you contract JVD to design your Analog iASIC, we don’t gouge you for high performance. We maintain fair margins, regardless of your requirements. If your Analog iASIC design has critical performance specifications, more than likely you will save a lot of money with JVD as your supplier.
Protect your ideas: Embedding your proprietary ideas into a custom IC is not a guarantee of security. Companies all over the world have techniques to buy an end product, de-capsulate a critical component and reverse engineer it. If yours is a Billion dollar idea, rest assured, someone will try it. They may even try it for a ten million dollar idea. It can’t be stopped, however what we can do is not give these evil minded forces a head start. By restricting the geographical distribution of your design, JVD reduces the chances of your IP falling into the wrong hands. All our design engineers are US citizens. We use vendors to make masks and foundries to make wafers that are located here on US soil. This reduces the chance of your ideas being pirated by those sinister sources.
The question is like asking; “How high is up?” Let us give you a quote – be sure to get one or more to compare. Will JVD always be the lowest cost? Probably not. But we own our building and all our equipment… 100% debt fee…and we have this habit of passing the associated lower overhead costs on to our customers. Don’t you hate it when that happens? Our competition hates it. Don’t be mislead. We do have some overhead, but our NRE (One time Non-Recurring Engineering) costs end up looking more like variable costs.
When we quote your design, we pair your needs with the best available engineer(s) in our talent pool… engineers who understand not just basic analog design, but the end applications and the subtleties most other chip designers don’t know about. We also consider this in the context of which fab process will best suite your product. We then design your chip to match the most optimum process that will offer you consistently high yields and thus the best price/performance ratio. And when it comes to the analog aspects of your design, we hand craft it so you’re not stuck with the fixed performances of a limited number of analog cells in someone’s library. Risky? Not really. Trust us; there are a lot of library based analog cells that don’t meet the specifications they claim…and there’s nothing any customer can do about that.
Yes, we use IP. Both Analog and Digital. It improves productivity, but we never let that supersede quality. There are hundreds of IP sources and few ASIC companies recognize that not all IP is created equal. Sourcing low cost IP (buying based only on price) can be dangerous. Our designers always verify the functional correctness of the IP design and how well it interfaces with any other IP that may be required. IP suppliers may claim their cells are silicon proven, but that does not mean it will perform perfectly in ‘your’ design. Remember, each cell was designed to be a general functional block. Most of the time this is sufficient. When it’s not, you want a team behind you and your IC that knows the difference… a team like JVD.
Not when you use JVD. We’ll tell you up front the risks involved and if failure (the ultimate risk) is one of them, we’ll not accept the project. It’s our reputation too. We’re not too proud to admit what we don’t think we can do. This rarely happens, but when it does, we’ll both feel better for not having gone thru the agony of a bad engagement. We have never accepted a design challenge we could not solve within budget and time.
Yes. Even though you have committed your design elsewhere, this is still a perfect time for JVD to get involved. We can assist with final verification and process compatibility, ensuring your design/process combination will meet your yield/cost expectations. Our verification process will alert you to pending issues and together we will implement the correct solutions prior to JVD taking the project to production. We will act as though we are a part of your company by being your virtual backend manufacturing and test operation. We can even arrange for the products to be shipped directly to your customers or distributors.
Yes. We have assumed projects mid stage and made them more manufacturable and more reliable. Sometimes it involves only a minor design or process change, but occasionally it can be more involved. We see these problems a lot with companies who ‘low ball’ the ASIC development price to entice a customer and then don’t have resources to support the effort in production. JVD’s team of experts will analyze your existing design, implement corrective procedures and supply you as a reliable source of products.
We can use any available foundry. But remember, these foundries are typically catering to the really large digital companies and their processes, although suitable for many basic analog functions, were developed primarily to optimize the digital IC’s “Axis of Evil” … ‘speed’, ‘density’ and ‘power’. If your design is Analog rich, your product may perform better in a fab whose process can be tweaked to match your design parameters. We like to call these companies boutique fabs. JVD typically uses boutique fabs located in Silicon Valley because we can meet directly with the fab process people, eliminate problems with wafer transportation, communicate in real time and have a strong sense of security about your IP. Years ago, companies were terrified of changing (tweaking) processes, but today, with better fab equipment, better analog modeling and smarter software tools, it’s quite common.